One technique of providing a 360.degree. adjustable delay to an incoming periodic signal is to use a tapped delay line shown in FIG. 1. The tapped delay line 110 is formed of delay elements each having some nominal delay and some quantifiable variation about the nominal delay. The desired delay is produced by selecting the appropriate tap 140 using a selection circuit 150 shown. To build a tapped delay line on an integrated circuit, the delay element is usually constructed from a semiconductor logic gate or pair of logic gates fabricated according to a specific process and subject to the variations in that process as well in environmental conditions. If a tapped delay line or delay chain is formed from these delay elements and it is desirable to be able to vary the delay of the incoming signal through its entire period, i.e., 360.degree., the number of delay elements in chain 110 must be determined based on the fastest delay for each element to assure that delays throughout the entire period of the incoming signal are selectable.
The location of the desired tap for a particular phase adjustment may vary due to process parameters varying the actual delay through the inverters from chip to chip. In addition, the actual clock frequency could vary, which would also change the tap needed for the desired phase adjustment. At high clock speeds, even small delay variations become significant, especially if accumulated through several delay elements.
Furthermore, if the delay chosen is equal to the input or output tap of chain 110, delay chains 100 and 120, each spanning at least half a period of the incoming signal, must be added to the beginning and the end of chain 110 to cover adjustments less than 0.degree. and greater than 360.degree.. The result is a delay chain which has a large number of delay elements.
For example, referring to FIG. 1, if the period of incoming clock 130 is 3.2 nanoseconds (ns) and if an inverting delay element is used (as is typical in CMOS circuitry) having a delay of 100 picoseconds (ps), then each tap 140 has a delay of 200 ps because taps in FIG. 1 have the same polarity. Thus 64 inverting delay elements are required as follows. Chain 110 has 16 taps (32 delay elements) to cover the 360.degree. period of the incoming clock. Chain 100 has 8 taps (16 delay elements) before chain 110 and chain 120 has 8 taps (16 delay elements) after chain 110 to cover adjustment at the phase boundaries of the incoming clock. The number of delay elements required is set by the fastest delay of a delay element and the largest clock period. However, the resolution of selectable delays for the output signal is determined by the slowest delay between taps. In a typical situation,the delay of one of the delay elements can vary by a factor of three between the slowest delay and the fastest delay.
Therefore, in the example above, the resolution of the selectable delays from the line is 600 ps, because two delay elements, each having a slowest delay of 300 ps, are required between each tap when using inverters as the delay elements.
Thus, the technique of a simple delay chain to provide a 360.degree. adjustable delay to an incoming periodic signal has several drawbacks. First is that it requires a large number of delay elements to span the period of the incoming clock. The large number of elements take up a good deal of space and consume significant power. Second, it has the resolution of the slowest delay between taps. This resolution may not be acceptable for certain applications. Third, it requires additional delay elements to cover adjustments at the phase boundaries, further compounding the space and power problem. Fourth, the large number of delay elements accumulates certain errors as the signal progresses down the chain causing more noise and jitter to the signals produced by the chain at the taps. For these and other reasons it is desirable to have a technique of producing a 360.degree. adjustable delay to an incoming periodic signal that has a small number of delay elements with better resolution than a simple tapped delay line.